Circuit structure

ABSTRACT

A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of and claims priority benefit of anU.S. application Ser. No. 12/181,556, filed on Jul. 29, 2008, now incondition of allowance. The prior U.S. application Ser. No. 12/181,556claims the priority benefit of Taiwan application serial no. 97119179,filed on May 23, 2008. The entirety of each of the above-mentionedpatent applications is hereby incorporated by reference herein and madea part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a circuit structure and amanufacturing method thereof, and more particularly, to a circuitstructure disposed on a circuit substrate and a manufacturing method ofthe circuit structure.

2. Description of Related Art

In this information society, people are pursuing products with highspeed, high quality and multifunction. As to the product appearance, itis trending toward light, thin and small. Typical electronic productsinclude a chip and a substrate (e.g., chip carrier) connected to thechip. The chip includes an active surface with a plurality of bumps(e.g., gold bumps) disposed thereon, and is electrically connected to acircuit structure of the substrate by flip-chip bonding. The chip canreceive a signal from or transmit a signal to the circuit structure ofthe substrate via the bumps. Therefore, the high reliability of theconnecting between the bumps and the circuit structure of the substrateis critically important to the quality of signal transmission.

In addition, a thermal stress may be generated between the chip and thesubstrate due to unmatched coefficient of thermal expansion. Therefore,an underfill is typically filled in between the chip and the substrateto enclose the bumps to avoid transverse crack of the bumps that couldresult from a long time influence by the thermal stress between the chipand the substrate.

FIG. 1 is a cross-sectional view of a conventional flip-chip packagestructure. Referring to FIG. 1, the chip 110 is disposed on a substrate120 by flip-chip bonding, and the chip 110 includes a plurality of bumps112 for electrically connecting to a circuit structure 122 of thesubstrate 120. A solder mask 130 is disposed on the substrate 120 forcovering a part of the circuit structure 122. Because the solder mask130 needs to protect this part of the circuit structure 122 from beinginfluenced during a soldering process, the solder mask 130 needs tomaintain a certain thickness. However, if the interval H1 between thechip 110 and the solder mask 130 is too small, the underfill 140 cannoteasily be filled in the interval between the chip 110 and the substrate120, which may affect the reliability of the connecting between thebumps 112 and the circuit structure 122 of the substrate 120. Whatneeded, therefore, is to increase the interval H1 between the chip 110and the solder mask 130.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method for making acircuit structure, through which the interval between a chip and asolder mask can be increased.

The present invention is also directed to a circuit structure which,when connected to a chip, has an increased interval between the chip anda solder mask.

The present invention provides a method for making a circuit structureas follows. Firstly, a base conductive layer is formed on a carrierboard. A first patterned plating-resistant layer is then formed on thebase conductive layer. The first patterned plating-resistant layercomprises at least one trench which exposes a part of the baseconductive layer. A first patterned conductive layer is formed in thetrench. Next, a second patterned plating-resistant layer is formed whichcovers the first patterned conductive layer and a part of the firstplating-resistant layer. The second patterned plating-resistant layercomprises an opening to expose a part of the first patterned conductivelayer. A second patterned conductive layer is then formed on the firstpatterned conductive layer that is exposed by the opening. Next, thefirst patterned plating-resistant layer and the second patternedplating-resistant layer are removed. The base conductive layer exposedby the first patterned conductive layer is removed. Finally, a patternedsolder mask is formed which covers a part of the first patternedconductive layer. The patterned solder mask comprises at least oneopening to expose the second patterned conductive layer and a part ofthe first patterned conductive layer adjacent to the second patternedconductive layer.

According to one embodiment of the present invention, the material ofthe first patterned conductive layer is one of copper, aluminum, gold,platinum, nickel, silver, tin, alloy of the above metals, and anycombination thereof.

According to one embodiment of the present invention, the material ofthe second patterned conductive layer is the same as the material of thefirst patterned conductive layer.

According to one embodiment of the present invention, the material ofthe first patterned plating-resistant layer and the second patternedplating-resistant layer comprises a photosensitive material.

According to one embodiment of the present invention, the firstpatterned conductive layer is formed by a plating process, a physicaldeposition process, or a chemical deposition process.

According to one embodiment of the present invention, the secondpatterned conductive layer is formed by a plating process, a physicaldeposition process, or a chemical deposition process.

The present invention also provides a circuit structure suitable forbeing disposed on a carrier board. The circuit structure comprises afirst patterned conductive layer, a second patterned conductive layer,and a solder mask. The first patterned conductive layer is disposed onthe carrier board. The second patterned conductive layer is disposed ona part of the first patterned conductive layer. A part of the edge ofthe second patterned conductive layer and a part of the edge of thefirst patterned conductive layer are substantially coplanar. Thepatterned solder mask covers a part of the first patterned conductivelayer and has at least one opening for exposing the second patternedconductive layer and a part of the first patterned conductive layeradjacent to the second patterned conductive layer.

According to one embodiment of the present invention, the material ofthe first patterned conductive layer is one of copper, aluminum, gold,platinum, nickel, silver, tin, alloy of the above metals, and anycombination thereof.

According to one embodiment of the present invention, the material ofthe second patterned conductive layer is the same as the material of thefirst patterned conductive layer.

According to one embodiment of the present invention, the circuitstructure further comprises a base conductive layer disposed between thefirst patterned conductive layer and the carrier board.

In summary, since in the circuit structure of the present invention, thesecond patterned conductive layer is only formed at locations where thecircuit structure and bumps of the chip are connected, and the patternedsolder mask merely covers the first patterned conductive layer.Therefore, the second patterned conductive layer not only can raise theheight of the solder pad, but also can increase the interval between thechip and the patterned solder mask, thereby overcoming the problem inthe prior art that the underfill is difficult to fill in the intervalbetween the chip and the solder mask due to the small interval betweenthe chip and the solder mask.

In order to make the aforementioned and other features and advantages ofthe present invention more comprehensible, embodiments accompanied withfigures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional circuit structure.

FIGS. 2A through 2G are perspective views illustrating a process formaking a circuit structure according to one embodiment of the presentinvention.

FIG. 3 is a cross-sectional view of a flip-chip package structure formedby a circuit structure according to one embodiment of the presentinvention and a chip.

DESCRIPTION OF THE EMBODIMENTS

FIGS. 2A through 2G are perspective views illustrating a process formaking a circuit structure according to one embodiment of the presentinvention.

Referring to FIG. 2A, firstly, a base conductive layer 210 is formed ona carrier board 202. In various embodiments of the present invention,the carrier board 202 may be, for example, a dielectric substrate, asingle layer circuit substrate, or a multi-layered circuit substrate. Inthis illustrated embodiment, the carrier board 202 is illustrated as adielectric substrate for the purpose of description only and should notbe regarded as limiting. The base conductive layer 210 may be formed byelectroless plating or physical vapor deposition. The electrolessplating may be, for example, chemical deposition of copper film. Thematerial of the base conductive layer 210 may be, for example, one ofcopper, aluminum, gold, platinum, nickel, tin, alloy of the abovemetals, or any combination thereof, or alternatively be another suitableconductive material.

Next, as shown in FIG. 2A, a first patterned plating-resistant layer 220is formed on the base conductive layer 210. The first patternedplating-resistant layer 220 has at least one trench 222 which exposes apart of the base conductive layer 210. The material of the firstpatterned plating-resistant layer 220 is, for example, a photosensitivematerial, such as, a dry film or a liquid film. In case thephotosensitive material is the dry film, the first patternedplating-resistant layer 220 may be formed, for example, by firstattaching a layer of photosensitive material on the base conductivelayer 210 and subsequently patterning the photosensitive material layer.In case the photosensitive material is the liquid film, the firstpatterned plating-resistant layer 220 may be formed, for example, byfirst coating a layer of photosensitive material on the base conductivelayer 210 and subsequently patterning the photosensitive material layer.The patterning process used herein includes an exposure and developmentprocess or a photo etching process, or the like. The photo etchingprocess includes using a light source, such as, an ultraviolet light, aninfrared light or an excimer laser, to directly form the trench 222 inthe photosensitive material layer.

Afterwards, referring to 2B, a first patterned conductive layer 230 isformed in the trench 222. In the illustrated embodiment, the firstpatterned conductive layer 230 is, for example, a circuitry layer. Inaddition, in the illustrated embodiment, the first patterned conductivelayer 230 may be formed by a plating process or an electroless platingprocess. The electroless plating process may be a physical deposition ora chemical deposition. It is noted that, since the first patternedplating-resistant layer 220 is formed on the base conductive layer 210,in the illustrated embodiment, the first patterned conductive layer 230may be formed in a specific area (i.e., the area exposed by the trench222) on the base conductive layer 210 by using the plating process orthe electroless plating process. In various embodiments of the presentinvention, the material of the first patterned conductive layer 230 maybe, for example, one of copper, aluminum, gold, platinum, nickel,silver, tin, alloy of the above metals, and any combination thereof, oralternatively be another suitable conductive material.

Next, referring to FIG. 2C, a second patterned plating-resistant layer240 is formed on the first patterned conductive layer 230 and a part ofthe first patterned plating-resistant layer, 220. The second patternedplating-resistant layer 240 has at least one first opening 242 forexposing a part of the first patterned conductive layer 230. The secondpatterned plating-resistant layer 240 may be formed in the same way asthe first patterned plating-resistant layer 220. The material of thesecond patterned plating-resistant layer 240 may be a photosensitivematerial such as a dry film or a liquid film.

Next, referring to FIG. 2D, a second patterned conductive layer 250 isformed on the first patterned conductive layer 230 that is exposed bythe first opening 242 of the second patterned plating-resistant layer240. In the illustrate embodiment, the second patterned conductive layer250 may be formed in the same way as the first patterned conductivelayer 230. It is noted that, since the second patternedplating-resistant layer 240 covers a part of the first patternedconductive layer 230, the second patterned conductive layer 250 can beselectively formed in a specific area on the first patterned conductivelayer 230 (i.e., the area exposed by the first opening 242).

In addition, the material of the second patterned conductive layer 250may be, for example, one of copper, aluminum, gold, platinum, nickel,silver, tin, alloy of the above metals, and any combination thereof, oralternatively be another suitable conductive material. Besides, in theillustrated embodiment, the material of the first patterned conductivelayer 230 may be the same as the material of the second patternedconductive layer 250.

Afterwards, referring to FIG. 2E, the first patterned plating-resistantlayer 220 and the second patterned plating-resistant layer 240 areremoved. Subsequently, referring to FIG. 2F, the base conductive layer210 exposed by the first patterned conductive layer 230 is removed byusing, for example, an etching process.

Next, referring to FIG. 2G, a patterned solder mask 260 is formed tocover a part of the first patterned conductive layer 230. The patternedsoldering layer 260 includes at least one second opening 262 forexposing the second patterned conductive layer 250 and a part of thefirst patterned conductive layer 230 adjacent to the second patternedconductive layer 250. In this illustrated embodiment, the patternedsolder mask 260 may be formed by, for example, an ink jet printingprocess or a traditional image transfer process which involves coatingof a soldering-resistant material and a subsequent exposure anddevelopment process. The first patterned conductive layer 230, thesecond patterned conductive layer 250, and the patterned solder mask 260collectively form a circuit structure 300.

In addition, in the illustrated embodiment, the surfaces of theconductive layers 210, 230, 250 exposed by the solder mask 260 aresubjected to a surface anti-oxidation treatment to form ananti-oxidation layer (not shown). These anti-oxidation layers canprevent oxidation of the exposed conductive layer 210, 230, 250. Thematerial of the anti-oxidation layer may be one of nickel and gold,silver, tin, organic solderability preservative (OSP), and anycombination thereof, or alternatively be another suitable anti-oxidationmaterial.

The construction of the circuit structure 300 is described in greaterdetail below.

Referring to FIG. 2G, the circuit structure 300 includes a firstpatterned conductive layer 230, a second patterned conductive layer 250,and a patterned solder mask 260. The first patterned conductive layer230 is disposed on a carrier 202. In various embodiments of the presentinvention, the carrier 202 may be, for example, a dielectric substrate,a single-layered circuit substrate or multi-layered circuit substrate.

The second patterned conductive layer 250 is disposed on a part of thefirst patterned conductive layer 230, with a part of an edge 252 of thesecond patterned conductive layer 250 and a part of an edge 232 of thefirst patterned conductive layer 230 are coplanar. For example, in theillustrated embodiment, the first patterned conductive layer 230 has afirst sidewall 234, and the second patterned conductive layer 250 has asecond sidewall 254 substantially coplanar with the first sidewall 234.

In addition, in the illustrated embodiment, the material of the firstpatterned conductive layer 230 may be the same as the material of thesecond patterned conductive layer 250. Besides, in the illustratedembodiment, a base conductive layer 210 may further be disposed betweenthe first patterned conductive layer 230 and the carrier board 202. Thematerial of the base conductive layer 210 is, for example, one ofcopper, aluminum, gold, platinum, nickel, tin, alloy of the abovemetals, and any combination thereof, or alternatively be anothersuitable conductive material. Furthermore, the material of the baseconductive layer 210 is, for example, the same as the material of thefirst patterned conductive layer 230 and the second patterned conductivelayer 250 (e.g., the material of the base conductive layer 210, firstconductive layer 230 and second conductive layer 250 are all copper).

A patterned solder mask 260 is formed to cover a part of the firstpatterned conductive layer 230. The patterned solder mask 260 has atleast one second opening 262 for exposing the second patternedconductive layer 250 and a part of the first patterned conductive layer230 adjacent to the second patterned conductive layer 250. The secondpatterned layer 250 and the portion of the first patterned conductivelayer 230 adjacent to the second patterned conductive layer 250, whichare exposed by the second opening 262, may be used as a solder pad Psuitable for being connected to bumps of a chip (not shown).

FIG. 3 is a cross-sectional view of a flip-chip package structure formedby a circuit structure according to one embodiment of the presentinvention and a chip. Referring to FIG. 3, the circuit structure 300 ofthis embodiment is the same as the circuit structure 300 shown in FIG.2G and, therefore, its construction is not repeated herein. The chip 410has an active surface 412 with a plurality of bumps 414 formed thereon.While two bumps 414 are shown in FIG. 3, the number of the bumps 414should not be limited to two and, thus, in other embodiments, the numberof the bumps 414 could be more than two. The bumps 414 extend into thesecond openings 262 of the patterned solder mask 260 to be connected tothe second patterned conductive layer 250.

Since in the circuit structure 300 of the illustrated embodiment, thesecond patterned conductive layer 250 is only formed at locations wherethe circuit structure 300 and the bumps 414 are connected, the secondpatterned conductive layer 250 can raise the thickness of the solder padP thus increasing the height of the solder pad P. In addition, thepatterned solder mask 260 merely covers the first patterned conductivelayer 230. Therefore, when the height of the solder pad P is raised bythe second patterned conductive layer 250, the height of the patternedsolder mask 260 will not be increased correspondingly. As a result, theincreased height of the solder pad P raised by the second patternedconductive layer 250 can increase the interval H2 between the chip 410and the patterned solder mask 260, thus facilitating filling theunderfill 420 in the interval between the chip 410 and the patternedsolder mask 260.

In summary, since in the circuit structure of the present invention, thesecond patterned conductive layer is only formed at locations where thecircuit structure and bumps of the chip are connected, and the patternedsolder mask merely covers the first patterned conductive layer.Therefore, the second patterned conductive layer not only can raise theheight of the solder pad, but also can increase the interval between thechip and the patterned solder mask, thus facilitating filling theunderfill in the interval between the chip and the patterned soldermask, so as to raise the reliability of the connection between bumps ofa chip and the circuit structure.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A circuit structure, suitable for being disposed on a carrier board, comprising: a first patterned conductive layer disposed on the carrier board; a second patterned conductive layer disposed on a part of the first patterned conductive layer, a part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar; and a patterned solder mask covering a part of the first patterned conductive layer, the patterned solder mask having at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.
 2. The circuit structure according to claim 1, wherein the material of the first patterned conductive layer is one of copper, aluminum, gold, platinum, nickel, silver, tin, alloy of the above metals, and any combination thereof.
 3. The circuit structure according to claim 1, wherein the material of the second patterned conductive layer is the same as the material of the first patterned conductive layer.
 4. The circuit structure according to claim 1, further comprising a base conductive layer disposed between the first patterned conductive layer and the carrier board. 